In conventional active matrix liquid crystal display devices, thin film transistors (hereinafter called “TFT”) are utilized as switching elements in pixel formation portions. In recent years, however, TFT has been used not only as switching elements in pixel formation portions but also as elements for drive circuits, even in liquid crystal display devices manufactured from large substrates of newer generations including the sixth generation substrates, in an effort to reduce the manufacturing cost. In this trend, development has been made for changing the TFT's channel layers from conventional amorphous silicon layers to microcrystalline silicon layers for improved characteristics.
However, the TFT utilizing microcrystalline silicon layers as its channel layer has a problem that when the TFT is turned OFF, a current which flows between the source electrode and the drain electrode (hereinafter called “Off-state current”) is greater than in those TFTs utilizing amorphous silicon layers as their channel layers. In an attempt to solve this, Japanese Laid-Open Patent Publication No. 9-92841 discloses a bottom-gate TFT which makes use of a stacked film constituted by an amorphous silicon layer and a microcrystalline silicon layer as a channel layer.
FIG. 20 is a sectional view showing a configuration of a conventional bottom-gate TFT 600 disclosed in Japanese Laid-Open Patent Publication No. 9-92841, in which a microcrystalline silicon layer 645 and an amorphous silicon layer 630 form a stacked film serving as a channel layer 640. As shown in FIG. 20, the TFT 600 has a glass substrate 601, on which a gate electrode 660 is formed, and the entire glass substrate 601 including the gate electrode 660 is covered by a gate insulation film 650. The microcrystalline silicon layer 645 is formed on the gate insulation film 650. The amorphous silicon layer 630 is formed on the microcrystalline silicon layer 645. The microcrystalline silicon layer 645 and the amorphous silicon layer 630 constitute a stacked film which serves as a channel layer 640 of the TFT 600. A left and a right ends of the amorphous silicon layer 630 are respectively formed with ohmic contact layers 620, 621 doped with high concentration n-type impurities, and on these ohmic contact layers 620, 621, a source electrode 610 and a drain electrode 612 are formed respectively. Further, the entire TFT 600 is covered by a protective layer 670.